1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit processing, and more specifically to an improved method for forming features having critical dimensions, such as transistor gates in an integrated circuit.
2. Description of the Related Art
Semiconductor manufacturing is capital intensive and extremely competitive. Survival of semiconductor manufacturing concerns depends on constant innovation to produce more components at lower costs. New device designs often require additional capital investment in order to fabricate the new designs, as is explained below in more detail.
The manufacturing cost of an integrated circuit depends in part on how much semiconductor area is required to implement desired functions. The area, in turn, is defined by geometries and sizes of elements of active components such as FET gates and by diffused or implanted regions such as FET sources and drains and bipolar transistor emitters and bases.
The smallest features in many devices have a critical dimension that is often similar in size to the wavelengths of light used to photolithographically define the feature. As a result, further reduction of the size of the critical dimension may require new equipment, using either shorter light wavelengths or techniques not dependent on light for feature definition (e.g., using focused electron beams). Capital costs of several tens of million dollars each are not unusual for these types of equipment.
Maximum operating frequency is a figure of merit for integrated circuits and is determined by a confluence of factors. Parasitic capacitance in transistors making up the integrated circuits strongly affects maximum operating frequency. Higher operating frequencies also tend to require smaller feature sizes for a variety of reasons. As a result, design techniques that reduce parasitic capacitance or that result in smaller feature sizes can be extremely valuable to semiconductor manufacturers.